1. Field of the Invention
The present invention relates to a semiconductor device.
2. Related Art
Conventionally, the flip-flop circuit composed of a CMOS circuit as a standard cell has included two built-in clock generating inverters which turn on/off gates of both a transmission gate and a clocked inverter. Those clock generating inverters have been arranged together frequently. In this case, diffusion regions of those clock generating inverters have been separated from the other diffusion regions, so that it has been necessary to form a lot of shallow trench isolation (STI) regions, as element isolation regions, in the flip-flop circuit.
For example, in a flip-flop disclosed in FIG. 1 of Japanese Patent Application Laid-Open No. 2001-332626, two inverters (clock generating inverters) that are supplied with a clock signal CK to generate clock signals CK0/XCK0 respectively are arranged together in such a manner that they may share the same source region. The inverters have required an STI region on both sides thereof.
Thus, conventionally, a lot of STI regions have been formed to increase the cell size of the flip-flop circuit. Therefore, there has been a problem in that the large size of the flip-flop circuits, which occupy about 40% of a logic region of an IC chip, increases the chip size.
Further, as disclosed in Japanese Patent Application Laid-Open No. 11-55081, a pulse generation circuit (clock generating inverter) can be arranged outside of a plurality of flip-flops so that the pulse generation circuit may be common to those flip-flops, thereby decreasing the area of the flip-flops. However, long interconnections are required between each of the flip-flops and the pulse generation circuit to give rise to a difference in phase between clock pulses applied to those flip-flops, thus resulting in a problem of malfunctioning thereof.